SPArc-subset general-purpose microprocessor design and implementation in field programmable gate array
Main Article Content
Abstract
This paper focuses on designing a 32-bit Reduced Instruction Set Computer (RISC) Scalable Processor Architecture (SPArc) subset gener al purposes processor. The design process covers instructions selection, Register Transfer Notation (RTN) design, Datapath Design, and Control Unit Design. Basic integer instruction was selected. Datapath was designed along with the RTN with a five-stage pipeline with direct connection between stages. This design was then validated using functionality simulation test and implemented in Field Programmable Gate Array (FPGA). The performance of the processor was measured using thermal report, power report, and time report. Functional test shows that the Processor can execute instructions as designed, which are Arithmetic/Shift/Logic, Control Transfers, and Memory access instructions. It was validated with the register content and signal generated in each stage. The design was also successfully implemented in FPGA with the maximum clock of 58 MHz as the synthesis report shows. Thermal report shows the thermal properties of the design, which shown the acceptable thermal margin of 56.9 ?C and junction temperature of 28.1 ?C. The power report shows the low power consumption of 0.266 W, which consists of dynamic power of 0.173 W and static power of 0.093 W. This work enables further development and to be used as master processor in System on Chip design of special purpose processors like cognitive processors
Downloads
Download data is not yet available.
Article Details
How to Cite
Bachri, K. O. ., Alexander, J. ., Osmond, E. ., Widawati, E. . and Kartawidjaja, M. A. . (2024) “SPArc-subset general-purpose microprocessor design and implementation in field programmable gate array”, Jurnal Mantik, 8(3), pp. 1447-1455. doi: 10.35335/mantik.v8i3.5681.
References
Bachri, K. O., Khayam, U., Soedjarno, B. A., Sumari, A. D. W., & Ahmad, A. S. (2019). Cognitive artificial-intelligence for doernenburg dissolved gas analysis interpretation. Telkomnika (Telecommunication Computing Electronics and Control), 17(1), 268–274. https://doi.org/10.12928/TELKOMNIKA.v17i1.11612
Fengler, A., Jung, P., & Caire, G. (2021). SPARCs for Unsourced Random Access. IEEE Transactions on Information Theory, 67(10), 6894–6915. https://doi.org/10.1109/TIT.2021.3081189
Frühauf, J.-L., Hawich, M., & Blume, H. (2024). Enhancing RISC-V Processor Performance in Harsh Environments through Data Cache Optimization. 2024 Panhellenic Conference on Electronics & Telecommunications (PACET), 1–4. https://doi.org/10.1109/PACET60398.2024.10497077
Hemanthkumar, P. B., Anireddy, S. R., T, J. F., & R, V. (2022). Introduction to ARM processors & its types and Overview to Cortex M series with deep explanation of each of the processors in this Family. 2022 International Conference on Computer Communication and Informatics (ICCCI), 1–8. https://doi.org/10.1109/ICCCI54379.2022.9740768
Hennessy, J. L., & Patterson, D. A. (2019). Computer Architecture: A Quantitative Approach (6th ed.). Elsevier Inc.
Hepola, K., Multanen, J., & Jääskeläinen, P. (2024). Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode. IEEE Transactions on Computers, 73(2), 560–573. https://doi.org/10.1109/TC.2023.3337313
Hidri, L., Al-Samhan, A. M., & Mabkhot, M. M. (2019). Bounding Strategies for the Parallel Processors Scheduling Problem with No-Idle Time Constraint, Release Date, and Delivery Time. IEEE Access, 7, 170392–170405. https://doi.org/10.1109/ACCESS.2019.2954905
Jyotsna, K. A., Siddharth, S. S., Kumar, P. S., & Madhavi, B. K. (2022). Design of 32-Bit ARM Processor Data Path Units utilizing DVS Current Mode Technique. 2022 IEEE International Symposium on Smart Electronic Systems (ISES), 263–266. https://doi.org/10.1109/iSES54909.2022.00060
Kulshreshtha, A., Moudgil, A., Chaurasia, A., & Bhushan, B. (2021). Analysis of 16-Bit and 32-Bit RISC Processors. 2021 7th International Conference on Advanced Computing and Communication Systems, ICACCS 2021, 1318–1324. https://doi.org/10.1109/ICACCS51430.2021.9441873
Lindholm, T., Yellin, F., Bracha, G., & Buckley, A. (2014). The Java® Virtual Machine Specification, Java SE 8 Edition-Addison-Wesley Professional (8th ed.). Oracle.
Malatesta, F., Weigand, R., & Andersson, J. (2023). GR765: SPARC and RISC-V Multiprocessor System-on-Chip. 2023 European Data Handling & Data Processing Conference (EDHPC), 1–4. https://doi.org/10.23919/EDHPC59100.2023.10396360
Meyer-Baese, U. (2021). Embedded Microprocessor System Design using FPGAs. In Embedded Microprocessor System Design using FPGAs. Springer International Publishing. https://doi.org/10.1007/978-3-030-50533-2
Naffziger, S., Lepak, K., Paraschou, M., & Subramony, M. (2020). AMD Chiplet Architecture for High-Performance Server and Desktop Products. 2020 IEEE International Solid-State Circuits Conference (ISSCC 2020), 570. https://doi.org/10.1109/ISSCC19947.2020.9063103
Phangestu, A. E., Mujiono, I. T., Kom, M. I., & Zaini, S. A. (2022). Five-Stage Pipelined 32-Bit RISC-V Base Integer Instruction Set Architecture Soft Microprocessor Core in VHDL. 2022 International Seminar on Intelligent Technology and Its Applications (ISITIA), 304–309. https://doi.org/10.1109/ISITIA56226.2022.9855292
Pomianowski, A. (2021). RDNATM 2 Gaming Architecture. 2021 IEEE Hot Chips 33 Symposium (HCS), 1–18. https://doi.org/10.1109/HCS52781.2021.9567555
Rotem, E., Yoaz, A., Rappoport, L., Robinson, S. J., Mandelblat, J. Y., Gihon, A., Weissmann, E., Chabukswar, R., Basin, V., Fenger, R., Gupta, M., & Yasin, A. (2022). Intel Alder Lake CPU Architectures. IEEE Micro, 42(3), 13–19. https://doi.org/10.1109/MM.2022.3164338
Sakamoto, M., Katsuno, A., Inoue, A., Asakawa, T., Ueno, H., Morita, K., & Kimura, Y. (2002). Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems.
Savadatti, M. B., R, V., L, S. S. M., V, S., & Reddy, T. J. (2024). Data Transfer Using AMBA Bus: An Empirical Approach. 2024 2nd International Conference on Artificial Intelligence and Machine Learning Applications Theme: Healthcare and Internet of Things (AIMLA), 1–6. https://doi.org/10.1109/AIMLA59606.2024.10531613
Schöne, R., Ilsche, T., Bielert, M., Velten, M., Schmidl, M., & Hackenberg, D. (2021). Energy Efficiency Aspects of the AMD Zen 2 Architecture. 2021 IEEE International Conference on Cluster Computing (CLUSTER), 562–571. https://doi.org/10.1109/Cluster48925.2021.00087
Sereati, C. O., Sumari, A. D. W., Adiono, T., & Ahmad, A. S. (2020). Towards cognitive artificial intelligence device: An intelligent processor based on human thinking emulation. Telkomnika (Telecommunication Computing Electronics and Control), 18(3), 1475–1482. https://doi.org/10.12928/TELKOMNIKA.v18i3.14835
Soundari, D. V., Ganesh, M. K. S., Raman, I., & Karthick, R. (2021). Enhancing network-on-chip performance by 32-bit RISC processor based on power and area efficiency. Materials Today: Proceedings, 45, 2713–2720. https://doi.org/10.1016/j.matpr.2020.11.550
Suárez, D., Almeida, F., & Blanco, V. (2023). Comprehensive Analysis of Energy Efficiency and Performance of ARM and RISC-V SoCs. https://doi.org/10.21203/rs.3.rs-3405993/v1
Tang, G. M., Qu, P. Y., Ye, X. C., & Fan, D. R. (2018). Logic Design of a 16-bit Bit-Slice Arithmetic Logic Unit for 32-/64-bit RSFQ Microprocessors. IEEE Transactions on Applied Superconductivity, 28(4). https://doi.org/10.1109/TASC.2018.2799994
Vera, X. (2020). Inside Tiger Lake: Intel’s Next Generation Mobile Client CPU. 2020 IEEE Hot Chips 32 Symposium (HCS), 1–26. https://doi.org/10.1109/HCS49909.2020.9220443
Waterman, A., & Asanovi´c, K. A. (2017). The RISC-V Instruction Set Manual Volume I: User-Level ISA Document Version 2.2 Editors.
Xiang Lim, D., & G, S. K. (2019). Pipelined MIPS Simulation: A plug-in to MARS simulator for supporting pipeline simulation and branch prediction. In 2019 IEEE International Conference on Engineering, Technology and Education (TALE).
Yue, A., & Mehta, S. (2023). An Application-Oriented Approach to Designing Hybrid CPU Architectures. 2023 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 92–102. https://doi.org/10.1109/ISPASS57527.2023.00018
Zhang, W., Zhang, Y., & Zhao, K. (2021). Design and Verification of Three-stage Pipeline CPU Based on RISC-V Architecture. 2021 5th Asian Conference on Artificial Intelligence Technology (ACAIT), 697–703. https://doi.org/10.1109/ACAIT53529.2021.9731161
Fengler, A., Jung, P., & Caire, G. (2021). SPARCs for Unsourced Random Access. IEEE Transactions on Information Theory, 67(10), 6894–6915. https://doi.org/10.1109/TIT.2021.3081189
Frühauf, J.-L., Hawich, M., & Blume, H. (2024). Enhancing RISC-V Processor Performance in Harsh Environments through Data Cache Optimization. 2024 Panhellenic Conference on Electronics & Telecommunications (PACET), 1–4. https://doi.org/10.1109/PACET60398.2024.10497077
Hemanthkumar, P. B., Anireddy, S. R., T, J. F., & R, V. (2022). Introduction to ARM processors & its types and Overview to Cortex M series with deep explanation of each of the processors in this Family. 2022 International Conference on Computer Communication and Informatics (ICCCI), 1–8. https://doi.org/10.1109/ICCCI54379.2022.9740768
Hennessy, J. L., & Patterson, D. A. (2019). Computer Architecture: A Quantitative Approach (6th ed.). Elsevier Inc.
Hepola, K., Multanen, J., & Jääskeläinen, P. (2024). Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode. IEEE Transactions on Computers, 73(2), 560–573. https://doi.org/10.1109/TC.2023.3337313
Hidri, L., Al-Samhan, A. M., & Mabkhot, M. M. (2019). Bounding Strategies for the Parallel Processors Scheduling Problem with No-Idle Time Constraint, Release Date, and Delivery Time. IEEE Access, 7, 170392–170405. https://doi.org/10.1109/ACCESS.2019.2954905
Jyotsna, K. A., Siddharth, S. S., Kumar, P. S., & Madhavi, B. K. (2022). Design of 32-Bit ARM Processor Data Path Units utilizing DVS Current Mode Technique. 2022 IEEE International Symposium on Smart Electronic Systems (ISES), 263–266. https://doi.org/10.1109/iSES54909.2022.00060
Kulshreshtha, A., Moudgil, A., Chaurasia, A., & Bhushan, B. (2021). Analysis of 16-Bit and 32-Bit RISC Processors. 2021 7th International Conference on Advanced Computing and Communication Systems, ICACCS 2021, 1318–1324. https://doi.org/10.1109/ICACCS51430.2021.9441873
Lindholm, T., Yellin, F., Bracha, G., & Buckley, A. (2014). The Java® Virtual Machine Specification, Java SE 8 Edition-Addison-Wesley Professional (8th ed.). Oracle.
Malatesta, F., Weigand, R., & Andersson, J. (2023). GR765: SPARC and RISC-V Multiprocessor System-on-Chip. 2023 European Data Handling & Data Processing Conference (EDHPC), 1–4. https://doi.org/10.23919/EDHPC59100.2023.10396360
Meyer-Baese, U. (2021). Embedded Microprocessor System Design using FPGAs. In Embedded Microprocessor System Design using FPGAs. Springer International Publishing. https://doi.org/10.1007/978-3-030-50533-2
Naffziger, S., Lepak, K., Paraschou, M., & Subramony, M. (2020). AMD Chiplet Architecture for High-Performance Server and Desktop Products. 2020 IEEE International Solid-State Circuits Conference (ISSCC 2020), 570. https://doi.org/10.1109/ISSCC19947.2020.9063103
Phangestu, A. E., Mujiono, I. T., Kom, M. I., & Zaini, S. A. (2022). Five-Stage Pipelined 32-Bit RISC-V Base Integer Instruction Set Architecture Soft Microprocessor Core in VHDL. 2022 International Seminar on Intelligent Technology and Its Applications (ISITIA), 304–309. https://doi.org/10.1109/ISITIA56226.2022.9855292
Pomianowski, A. (2021). RDNATM 2 Gaming Architecture. 2021 IEEE Hot Chips 33 Symposium (HCS), 1–18. https://doi.org/10.1109/HCS52781.2021.9567555
Rotem, E., Yoaz, A., Rappoport, L., Robinson, S. J., Mandelblat, J. Y., Gihon, A., Weissmann, E., Chabukswar, R., Basin, V., Fenger, R., Gupta, M., & Yasin, A. (2022). Intel Alder Lake CPU Architectures. IEEE Micro, 42(3), 13–19. https://doi.org/10.1109/MM.2022.3164338
Sakamoto, M., Katsuno, A., Inoue, A., Asakawa, T., Ueno, H., Morita, K., & Kimura, Y. (2002). Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems.
Savadatti, M. B., R, V., L, S. S. M., V, S., & Reddy, T. J. (2024). Data Transfer Using AMBA Bus: An Empirical Approach. 2024 2nd International Conference on Artificial Intelligence and Machine Learning Applications Theme: Healthcare and Internet of Things (AIMLA), 1–6. https://doi.org/10.1109/AIMLA59606.2024.10531613
Schöne, R., Ilsche, T., Bielert, M., Velten, M., Schmidl, M., & Hackenberg, D. (2021). Energy Efficiency Aspects of the AMD Zen 2 Architecture. 2021 IEEE International Conference on Cluster Computing (CLUSTER), 562–571. https://doi.org/10.1109/Cluster48925.2021.00087
Sereati, C. O., Sumari, A. D. W., Adiono, T., & Ahmad, A. S. (2020). Towards cognitive artificial intelligence device: An intelligent processor based on human thinking emulation. Telkomnika (Telecommunication Computing Electronics and Control), 18(3), 1475–1482. https://doi.org/10.12928/TELKOMNIKA.v18i3.14835
Soundari, D. V., Ganesh, M. K. S., Raman, I., & Karthick, R. (2021). Enhancing network-on-chip performance by 32-bit RISC processor based on power and area efficiency. Materials Today: Proceedings, 45, 2713–2720. https://doi.org/10.1016/j.matpr.2020.11.550
Suárez, D., Almeida, F., & Blanco, V. (2023). Comprehensive Analysis of Energy Efficiency and Performance of ARM and RISC-V SoCs. https://doi.org/10.21203/rs.3.rs-3405993/v1
Tang, G. M., Qu, P. Y., Ye, X. C., & Fan, D. R. (2018). Logic Design of a 16-bit Bit-Slice Arithmetic Logic Unit for 32-/64-bit RSFQ Microprocessors. IEEE Transactions on Applied Superconductivity, 28(4). https://doi.org/10.1109/TASC.2018.2799994
Vera, X. (2020). Inside Tiger Lake: Intel’s Next Generation Mobile Client CPU. 2020 IEEE Hot Chips 32 Symposium (HCS), 1–26. https://doi.org/10.1109/HCS49909.2020.9220443
Waterman, A., & Asanovi´c, K. A. (2017). The RISC-V Instruction Set Manual Volume I: User-Level ISA Document Version 2.2 Editors.
Xiang Lim, D., & G, S. K. (2019). Pipelined MIPS Simulation: A plug-in to MARS simulator for supporting pipeline simulation and branch prediction. In 2019 IEEE International Conference on Engineering, Technology and Education (TALE).
Yue, A., & Mehta, S. (2023). An Application-Oriented Approach to Designing Hybrid CPU Architectures. 2023 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 92–102. https://doi.org/10.1109/ISPASS57527.2023.00018
Zhang, W., Zhang, Y., & Zhao, K. (2021). Design and Verification of Three-stage Pipeline CPU Based on RISC-V Architecture. 2021 5th Asian Conference on Artificial Intelligence Technology (ACAIT), 697–703. https://doi.org/10.1109/ACAIT53529.2021.9731161
Copyright and Licensing
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.